The present invention relates to embedded three-dimensional high capacitance density structures and methods for fabricating such structures.
Embedded ultra-high capacitance components are needed for applications such as noise suppression in high-speed circuits, high power electrode stimulators for implantable biomedical applications and miniaturized RF components. On-chip capacitance that take away valuable silicon real estate is needed to address high-frequency switching noise in today's digital circuits because package or board-level capacitors cannot be designed to provide low impedance power supply in the GHz frequency range. For mid-frequency decoupling, surface mount capacitors are required today because there is no available technology to embed high capacitance density films at package or board level. Similarly, for a typical biomedical neural stimulator application, approximately 10 μF is required to sustain operation of the stimulator without any reduction in voltage that could result in the failure of delivering the required stimulus current. For high electrode density implantable biomedical devices where miniaturization and low power are driving the components to be embedded on-chip or on-package, there is no available solution to provide the required capacitance density. New technologies, much beyond existing high-K (dielectric constant) thin film planar capacitors, are needed to address the emerging applications.
The choice of capacitor processing method is dependent on the constraints from integration (processing temperature) and cost (vacuum technology or solution deposition technologies), targeted capacitance density (capacitance per unit area), quality factor, operation frequency and breakdown voltage. The existing high K ceramic-polymer nanocomposite technology can only yield less than 5 nF/cm2 because it is inherently not capable of thin film (<3 microns) processing and high dielectric constant. Incorporating metallic fillers can give ultrahigh dielectric constant at the expense of quality factor and several other uncertainties. Ultrahigh K films generally yield lower dielectric strengths (<100 V/microns). They cannot be thinned to sub-100 nm without compromising the Breakdown Voltage.
High capacitance density thin films may be achieved with physical or chemical vapor deposited ferroelectric or super-paraelectric thin films. Simple planar (MIM) capacitors can only yield about 3-5 microafarad/cm2. FIGS. 1a and 1b and Table 1 illustrate that using higher K films does not correspondingly scale-up the capacitance density because breakdown voltages demand thicker films. High dielectric strength oxides, nitrides and oxynitrides can be thinned to 30 nm or so but their dielectric constant is insufficient. Thin film capacitors show insufficient capacitance density for several biomedical applications unless they are integrated onto 3D/high aspect ratio platforms. Certain biomimetic implants demand a capacitance density above 50 μF/cm2. To achieve ultrahigh capacitance densities, micromachined silicon and thermal oxidation/nitridation/oxynitridation of these silicon trenches are the most common options (FIGS. 2a and 2b) today. New innovations are needed to integrate higher capacitance densities in a low profile embedded capacitor format in organic or other substrates. Hence, there is an increasing demand for integrating 3D high dielectric constant structures on silicon or a compatible organic platform.
TABLE 1Thin film capacitor materials that can withstand 25 volts.High K ferroelectricsLower breakdown voltagesCapacitanceBarium titanaterequire thicker filmslimited toLead-based perovskitesK reduces with film thickness30 nF/mm2BST (few compositions)High K superparaelectricsDielectric constant low butCapacitanceStrontium titanate, BSTstable with lower losslimited to20 nF/mm2Moderate K paraelectricsHigher breakdown voltagesCapacitanceTantalum oxideallow thinner filmslimited to5 nF/mm2